The invention relates generally to a method for optimizing a routing of a signal path in a semiconductor device, and more specifically, to an optimization in terms of delay and signal integrity in a semiconductor device. The invention relates further to a related system for optimizing a routing of a signal path, and a computer program product.
Currently, at the end of an implementation phase (also called Engineering Changed Order phase) of macros/rows/units/course/chips one may have created an unrouteable netlist of routed netlists in which additional nets have to be implemented. In many times, these netlists have critical and uncritical nets, and during the implementation process annotations or tags of some of the nets are changed from critical to uncritical with respect to timing or signal integrity. But when these annotations have been changed they still use the same wire resources they needed at the beginning. To find additional wire resources in this phase of implementation, a work intensive manual process is necessary to take down uncritical and critical nets to find free resources (e.g., space for other wires) for new critical nets. In some cases, it is helpful to move buffers to other locations resulting in moving affected wires, too. However, the process starts with a selection of uncritical nets, a generation of a list of these nets, and taking down the used metal layer of these nets based on the available timing resources. Next, deleting the wiring and buffering follows before a re-run of a global routing process is performed. The so generated new nets have to be enhanced with the required buffers and then the detailed routing process has to be performed. When the routing is done, the netlist has to be extracted and atomic calculation on the extracted netlist is needed. This time-consuming, manual, iterative process is required multiple times, and in some cases, some nets have to be set to their original metal layer assignment in metal width because they do not have enough timing resources to be tagged down. Thus, such manual process may be a waste of time; it may increase the design layout process efforts and, thus effect the economic calculation negatively.